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cy27410 4-pll spread-spectrum clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-89074 rev. *k revised july 14, 2016 4-pll spread-spectrum clock generator features input frequencies ? crystal input: 8 mhz to 48 mhz ? reference clock: 8 mhz to 250 mhz lvcmos ? reference clock: 8 mhz to 700 mhz differential output frequencies ? 25 mhz to 700 mhz lvds, lvpecl, hcsl, cml ? 3 mhz to 250 mhz lvcmos ? 1 khz to 8 mhz for one lvcmos output rms phase jitter: 1-ps max at 12-khz to 20-mhz offset pcie 1.0/2.0/3.0 compliant sata 2.0, usb 2.0/3.0, 1/10-gbe compliant maximum 12 outputs split in tw o banks with six outputs each . ? up to eight differential outp ut pairs (hcsl, lvpecl, cml, or lvds) ? up to 12 lvcmos outputs up to 100-ps skew for differential outputs within a bank four fractional n-type phase-locked loops (plls) with ? vcxo (120 ppm with steps of 0.23 ppm) ? spread-spectrum capability (logic ss and lexmark profile 0.1% to 5% in 0.1% steps, down or center spread) supply voltage: 1.8 v, 2.5 v, and 3.3 v zero-delay buffer (zdb) and non-zero delay buffer (nzdb) configurations i 2 c configurable with onboard programming industrial-grade device, offered in 48-pin qfn (7 7 1.0 mm) package logic block diagram output drivers 1 pll1 o1[1..4] outc inc in1s in2s pll2 o2[1..4] inc in1s in2s pll3 o3[1..4] outc inc in1s in2s pll4 o4[1..4] inc in1s in2s o1[1..4] o2[1..4] o4[1..4] o3[1..4] output drivers 2 reference system in1s in2s ini inc in1p in1n in2p in2n register memory nv memory prg block adc fs i2c rcal rccal bg osc por qp ldos vin fs2 sclk sdat vdd fs1 fs0 out11p out11n out12p out12n out13p out13n out14p out14n vddio_d1 vddio_s1 out15 out16 out21p out21n out22p out22n out23p out23n out24p out24n vddio_d2 vddio_s2 out25 out26 xin xout
document number: 001-89074 rev. *k page 2 of 29 cy27410 contents functional description ..................................................... 3 input system ............................................................... 3 vcxo input block ....................................................... 3 frequency select input ............................................... 3 i2c block (sclk, sdat) ........ ..................................... 4 synthesis section ........................................................ 4 output section ............................................................. 4 onboard programming ................................................ 5 functional features and application considerations .......................................... 5 pinouts ............................................................................ 10 electrical specifications ................................................ 13 absolute maximum ratings .... ................................... 13 operating temperature ............................................. 13 operating power supply ........................................... 13 dc chip-level specifications .................................... 14 dc output specifications .......................................... 15 ac input clock specifications ................................... 16 ac output specifications .......................................... 16 test and measurement circuits ................................ 22 voltage and timing definition s ............ .............. ........ 23 packaging information ................................................... 25 solder reflow specifications ..................................... 25 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 29 worldwide sales and design s upport ......... .............. 29 products .................................................................... 29 psoc? solutions ...................................................... 29 cypress developer community ................................. 29 technical support ................. .................................... 29
document number: 001-89074 rev. *k page 3 of 29 cy27410 functional description the cy27410 is a standard-performance programmable clock generator with four independent fractional plls, which generates any frequency with a zero-ppm synthesis error. each pll is followed by a set of four independent dividers to generate four different frequencies from a single pll. all four dividers are synchronized to generate phase-aligned clock outputs with minimal skew. the plls also support the spread-spectrum feature to reduce emi. pll 1 has vcxo functionality to achieve ppm granularity of output frequency. the cy27410 accepts a crystal clock or a single-ended/differential reference clock. the device supports up to 12 outputs, divided into two banks with six outputs each. four outputs of pll 1 and pll 2 are multiplexed to output bank 1, and four clock outputs of pll 3 and pll 4 are multiplexed to output bank 2. the 12 outputs of the two banks are configurable as eight differential outputs, 12 single-ended outputs, or a combination of differential and single-ended outputs. the cy27410 has an on-chip volatile and nonvolatile memory, composed of eight register s, which store the device configuration settings. these registers can be accessed and programmed onboard through the i 2 c interface. you can also configure the device on-the-fly to completely reprogram the device on the application board. besides the i 2 c interface, external signals can be applied to multifunction pins for different functions such as the following: dynamically change the output frequency output enable/disable power down spread on/off one low-frequency clock output, in kilohertz, is provided to meet the need of widely used reference frequencies, such as 32.768 khz. the jitter specs of the cy27410 make it an ideal choice for the following communication protocols: pcie 1.0/2.0/3.0, usb 2.0/3.0, sata 1. 0/2.0, and 1/10gbe. input system the input system supports the following (see figure 1 ): xin/xout supports crystal input. in1 supports differential and single-ended clock inputs. in2 supports differential and single-ended clock inputs. figure 1. oscillator/clock input block diagram if a crystal is used, xin and xout are connected to a crystal oscillator to generate the required internal frequency, as shown in figure 2 . the supported differential tuning capacitor range is 8 pf to 12 pf. figure 2. connecting a crystal in1 and in2 are designed to accept either a single-ended or differential reference input. in2 can be used to accept the feedback signal to implement the zdb functionality of the device. the differential inputs are capable of interfacing with multiple standards, such as lvpecl, lvds, cml, and hcsl. the differential signals must be of ac-coupling, as shown in figure 3 . figure 3. interfacing differe ntial and single-ended signals vcxo input block the vin input is used for the vc xo functionality of the device. in this functionality, the outpu t can change with respect to an input voltage required for audio-visual applications. the output frequency can vary up to 120 ppm. this input voltage directly controls the pll 1 fractional divider to provide the vcxo functionality. frequency select input the cy27410 supports frequency-sele ct features with which the customer can change output freque ncies on-the-fly. the device has eight configuration register sets, which can be preprogrammed or written through i 2 c. changing the signal level of the fs pins (high and low) selects the appropriate configuration registers and changes the output frequency accordingly. mux div-r1 div-r2 in1p in2p xo inc ini in1s in2s in1n in2n to synthesis section xin xout xin xout xo crystal inxp inxn termination inxp inxn r s differential signal lvcmos signal 100 pf 100 pf
document number: 001-89074 rev. *k page 4 of 29 cy27410 i 2 c block (sclk, sdat) the cy27410 supports i 2 c programming of internal registers, which can be used to configure the device. the cy27410 also supports user-profile programming to flash memory and allows partial updates. read, write, or read/write protection is also available. the device is compliant with the i 2 c-bus specification, version 2.1 or later. the critical i 2 c specifications are as follows: 400 kb/s (fast mode) 7-bit addressing support selectable device address (programmable), default = 69 hex (7 bits) synthesis section the cy27410 contains four plls, which are the core synthesis blocks of the chip. each pll has a fractional n capability, which supports output frequency ge neration based on an input reference frequency to an accuracy of 100 ppb. the output of the pll is fed into four dividers and then moves to synchronizers to generate glitch-free clock tran sition features, variable delay generation circuits to support the programmable delay feature, and so on. the output dividers and multiplexers are also included as part of this subsystem. al l the four plls have the same architecture, as shown in figure 4 . figure 4. pll architecture output section the cy27410 has two banks of outp uts, which are located at the top and bottom of the device. ea ch bank consists of six outputs with out11?out14 and out21?out24 supporting both differential and single-ended outputs and out15?out16 and out25?out26 supporting only single-ended outputs. each output is fed from a pll through a divider and then to a mux, which helps in selecting the source for the output, as shown in figure 5 and figure 6 . figure 5. bank1 outputs figure 6. bank2 outputs inc in2s pdet + cp ox1 outc delay div ? o1 div ? o2 div ? o3 div ? o4 p \ path lf frac div n sync div ? c sync in1s ref fbk dly=0 \ 4 ? cycles ox2 ox3 ox4 i \ path lf vco div ? 2 div ? 2 div ? 2 div ? 2 sync sync sync sync div ? 2 5 div ? 2 sync out11 diff/se out12 out13 out14 diff/se diff/se diff/se out15 out16 se se o11 o12 o13 o14 o21 o22 o23 div i 1/2/4/8 div i 1/2/4/8 mux mux mux mux mux mux div l o24 ini out25 out26 out21 out22 out23 out24 diff/se diff/se diff/se diff/se se se o34 o33 o32 o31 o44 o43 o42 div i 1/2/4/8 div i 1/2/4/8 mux mux mux mux mux mux div l o41 ini
document number: 001-89074 rev. *k page 5 of 29 cy27410 onboard programming one can write the device memo ry on the customer board, enabling the use of a blank device that is not preprogrammed. this enables use of the same device across multiple projects and lets you program the device based on individual projects. conceptual onboard programming is shown in figure 7 . figure 7. onboard programming functional features and application considerations the cy27410 is a 4-pll spread-spectrum clock generator targeted at consumer, industrial, and low-end networking applications. the key specifications of the part are differential inputs (2) and outputs (12), supporting frequencies up to 700 mhz. the device has a low rms phase jitter of 1-ps max and value-added features, such as vcxo, frequency select, and pll bypass modes. this part is designed to support key standards, such as pcie 1.0/2.0/3.0, usb 2.0/3.0, and 10gbe. the product supports lvds, lvpecl, cml, hcsl, and lvcmos logic levels. clock generator the main feature of the cy27410 is frequency generation from an external reference (in1) or a crystal. there are four variables to determine the final output frequency. they are input ref, the div-r (r1), fracn (div-n) dividers, and the post dividers (div-o). the basic formula for determining the final output frequency is: clock generator mode ? f out = ((ref x div-n) / div-r) / div-o pll bypass mode ? f out = ref / div-i or ref / div-i / div-l the basic pll block diagram is shown in figure 8 . each of the outputs from the pll is fed to the output mux through a delay circuit that provides a certain delay to the individual clock, if needed. figure 8. pll block diagram, clock generation pcie (hcsl) clock generation for pcie applications, the cy27410 provides eight differential outputs that have the same spread on it at any particular point of time. vcxo and related frequencies the cy27410 provides vcxo functionality and a cascading pll option to generate critical freq uencies with a fixed reference. digital televisions have a requirement for the audio and video clocks to follow a 27-mhz vcxo signal so that they are synchronized. the architecture of the chip must ensure that this is met by cascading, as shown in figure 9 . figure 9. cascading plls apart from having the audio and video clocks following the 27-mhz vcxo input, they also need complex divider ratios to generate the output frequencies. commonly used divider ratios for audio and video signals are listed in ta b l e 1 . non volatile control ? store volatile control ? registers por, initialize i2c on ? board programming device configuration table 1. audio and video frequencies output frequency ratios 74.17582418 91:250 33.8688 625:784 22.5792 1875:1568 16.9344 1250:784 11.2896 1875:784 5.6448 1875:392 36.864 375:512 r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll vcfs (pll1) ss_pll pll pll xbuf 100mhz ? hcsl 66.66mhz ? lvcmos 27mhz ? vcxo video ? 74.25mhz audio ? 36.864mhz ref vin fs fs
document number: 001-89074 rev. *k page 6 of 29 cy27410 zero-delay buffer functionality the cy27410 acts as a zero-delay buffer (zdb) for one output from a single pll block. to implement this feature, take one of the outputs and send it back as a feedback reference to the pll. by providing a divider in the feedback loop, the device can also act as a frequency-multiplying zdb (see figure 10 ). this functionality is supported only when the pll is in the integer n mode. figure 10. zdb configuration the cy27410 provides the frequency-multiplying zdb by modulating the r1 and r2 values in the integer ratio. if both the values are identical, the cy27410 acts as a simple zdb. early/late output phase the cy27410 supports a delay circuit in the divider to provide 0 to 4 vco/2 cycles. therefore, an output has a certain lag phase or lead phase to other outputs when this feature is used. this functionality is also avail able in the zdb mode and provides ?early? phase or ?delayed? phase to the reference input. refer to figure 11 and figure 12 . figure 11. early/delayed phase output figure 12. early/late phase in zdb configuration non-zero delay buffer the cy27410 supports the pll-bypass mode, which bypasses the entire synthesis block to act as a configurable non-zero delay buffer (nzdb) with level translation and selectable inputs, as shown in figure 13 . figure 13. nzdb configuration combination clock generator and buffer the cy27410 provides a combination of a clock generator and a buffer in one device. this is achieved by configuring the input and output selectors for the desired split configuration. an example of such an application is shown in figure 14 . figure 14. clock generator and nzdb r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll ref r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll
document number: 001-89074 rev. *k page 7 of 29 cy27410 low-frequency output the cy27410 integrates low-frequency generator counters for lvcmos outputs that may be used for watchdog-time and/or khz-order clocks for application, as shown in figure 15 . figure 15. low-frequency output option spread spectrum to help reduce electromagnetic in terference (emi), the cy27410 supports spread-spectrum mo dulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies and lowe r system emi. the cy27410 implements two types of spread profiles for modulation: linear and nonlinear. the spread spectrum can be applied to any output clock, any frequency, and any spread amount ranging from 0.1% to 5% in 0.1% steps. the center or down spread can be programmable. the spread modulation rate is limited from 30 khz to 60 khz. the spread spectrum is generated digitally in the fracn modulation, which means all the parameters are independent of process, voltage, and temperatur e variations. all the frequencies generated by the same pll have the same amount of modulation. as shown in figure 16 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is de pendent on the harmonic number and the frequency deviation or spread. the equation for the reduction in the nonlinear profile is: db = 6.5 + 9 ?? log 10 (p) + 9 * log 10 (f) where p is the percentage of deviation and f is the frequency in megahertz where the reduction is measured. figure 16. spread-spectrum profile vcxo (vcfs) functionality the cy27410 supports vcxo functionality without pulling the crystal frequency. this function is implemented by modulating the fracn counter according to the vin level, as shown in figure 17 . therefore, this is called voltage-controlled frequency shift (vcfs). the vcfs function is implemented by modulating the fracn divider, which means all the parameters are independent of the process, voltage, and temperature variations. it is not possible to combine the vcfs operation with spread spectrum (see figure 18 ). figure 17. vcfs profile figure 18. vcfs and spread spectrum r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll max in frequency max min frequency amplitude (db) emi reduction typical clock ss clock frequency amplitude (db) emi reduction typical clock ss clock frequency linear profile nonlinear profile time time 0 vin 1/2 * vdd frequency ppm r1 r2 o1 o2 o3 o4 dly fracn pll c1 i1 i2 l1 synthesis block reference outputs from adjacent pll ssc vcfs vin
document number: 001-89074 rev. *k page 8 of 29 cy27410 crystal oscillator the cy27410 supports various low-cost crystals as a reference oscillator at in1 (xin/xout) to generate multiple frequencies in a single chip. the cy27410 supports a crystal with a nominal load capacitance specification from 8 pf to 12 pf. as shown in figure 2 on page 3 , the cy27410 integrates all the components, such as a feedback resistor and tuning capacitor, to oscillate the clock with a particular crystal for the following specifications. to enable proper operation, the crystal specification is divided into three ranges: low range (f nom ) = 8 to 12 mhz midrange = 12 to 20 mhz high range = 20 to 48 mhz the corresponding crystal parameters are listed in table 2 . serial programming interface protocol the cy27410 uses the sdat and sclk pins for a 2-wire serial interface that operates up to 400 kb/s in read and write modes. it complies with the i 2 c bus standard. the basic write protocol is: start bit; 7-bit device address; r/w bit; slave clock acknowledge (ack); 8-bit memo ry address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; and more until stop bit. the basic serial format is shown in figure 19 . figure 19. data transfer sequence on the serial bus a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (sdat = 0/low). the next eight bits must contain the data word intended for storage. after the data word is received, the slave responds with another acknowledge bit (sdat = 0/low), and the master must end the write sequence with a stop condition (see figure 20 ). figure 20. data frame architecture (write) table 2. crystal specifications range min frequency (mhz) max frequency (mhz) max r1 (ohms) max dl (uw) low 8 12 150 100 mid 12 20 70 100 high 20 48 50 100 c l (pf) for all ranges associated max c 0 (pf) 8 2 9 2 10 2 12 3 sclk sdat start condition address or acknowledge valid data may be changed stop condition write ack device address start memory address ack memory data ack memory data ack stop write ack device address start memory address ack memory data ack stop random write sequential write
document number: 001-89074 rev. *k page 9 of 29 cy27410 read operations are initiated the same way as write operations, except that the r/w bi t of the slave address is set to ?1? (high). there are two basic read operations: random read and sequential read. figure 21 illustrates these operations. figure 21. data frame architecture (read) through random read operations, the master may access any memory location. to perform this type of read operation, first set the word address. send the addre ss to the cy27410 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. next, the master reissues the control byte with the r/w byte set to ?1?. then, the cy27410 issues an acknowledge and transmits the 8-bit word. the master device does not acknowledge the transfer, but does generate a stop condition, which causes the cy27410 to stop transmission. sequential read operations follow the same process as random reads, except that the master i ssues an acknowledge instead of a stop condition after transmission of the first 8-bit data word. this action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. by continuing to issue acknowledges instead of stop conditions, the master may serially read the entire contents of the slave device memory. write ack device address start memory address ack ack device address start read memory data nack stop write ack device address start memory address ack ack device address start read memory data ack ack memory data nack stop random read sequential read
document number: 001-89074 rev. *k page 10 of 29 cy27410 pinouts the cy27410 devices are available in the 48-pin qfn package. table 3. cy27410 pin definitions name i/o type # of pins pin # function xin i crystal 1 8 xin for crystal xout o crystal 1 9 xout for crystal in1p i lvcmos/ differential 1 6 true input for in1 differential pair. in1 for lvcmos input. need external series capacitor for differential input. in1n i differential 1 5 complement input for in1 differential pair. none for lvcmos input. need external series ca pacitor for differential input. in2p i lvcmos / differential 1 4 feedback input for zdb mode. true input for in2 differential pair. in2 for lvcmos input need external series c aps for differential input. in2n i differential 1 3 feedback input for zdb mode. complement input for in2 differential pair. none for lvcmos input . need external series caps for differential input. out15 o lvcmos 1 39 lvcmos clock output 15 out16 o lvcmos 1 37 lvcmos clock output 16 out11p o lvcmos / differential 1 48 output 11 true output (differential) or output 11 lvcmos out11n o differential 1 47 output 11 complement output (differential) connect to out11p for lvcmos out12p o lvcmos / differential 1 46 output 12 true output (differential) or lvcmos clock output 12 out12n o differential 1 45 output 12 complement output (differential) connect to out12p for lvcmos out13p o lvcmos / differential 1 43 output 13 complement output (differential) or output 13 lvcmos out13n o differential 1 42 output 13 complement output (differential) connect to out13p for lvcmos out14p o lvcmos / differential 1 41 output 14 true output (differential) or output 14 lvcmos output out14n o differential 1 40 output 14 complement output (differential) connect to out14p for lvcmos out21p o lvcmos / differential 1 13 output 21 true output (differential) or output 21 lvcmos output out21n o differential 1 14 output 21 complement output (differential) connect to out21p for lvcmos out22p o lvcmos / differential 1 15 output 22 true output (differential) or output 22 lvcmos output out22n o differential 1 16 output 22 complement output (differential) connect to out22p for lvcmos out23p o lvcmos / differential 1 18 output 23 true output (differential) or output 23 lvcmos output out23n o differential 1 19 output 23 complement output (differential) connect to out23p for lvcmos
document number: 001-89074 rev. *k page 11 of 29 cy27410 out24p o lvcmos / differential 1 20 output 24 true output (differential) or output 24 lvcmos output out24n o differential 1 21 output 24 complement output (differential) connect to out24p for lvcmos out25 o lvcmos 1 22 lvcmos clock output 25 out26 o lvcmos 1 24 lvcmos clock output 26 dnu 1 10 pin for test purpose sdat i/o lvcmos / open drain 133i 2 c serial data pin sclk i lvcmos 1 34 i 2 c clock pin fs0 i lvcmos 1 30 frequency select pin fs1 i lvcmos 1 31 frequency select pin fs2 i lvcmos 1 32 frequency select pin vin i analog 1 26 voltage input for adc vddio_d1 pwr pwr 1 44 output power supply for bank 1 differential outputs vddio_s1 pwr pwr 1 38 output power supply for bank 1 lvcmos outputs vddio_d2 pwr pwr 1 17 output power supply for bank 2 differential outputs vddio_s2 pwr pwr 1 23 output power supply for bank 2 lvcmos outputs vdd pwr pwr 9 1, 2, 7, 11, 12, 25, 29, 35, 36 core power supply xres i lvcmos 1 27 active low reset signal gnd gnd gnd e-pad supply ground vccd analog analog 1 28 for 1.8-v operation, connect to vdd. for 2.5-v or 3.3-v operation, do not connect to vdd; connect a 100-nf capacitor between this pin and gnd. table 3. cy27410 pin definitions (continued) name i/o type # of pins pin # function
document number: 001-89074 rev. *k page 12 of 29 cy27410 figure 22. 48-pin qfn pinout out11p out11n out12p out12n out13p out13n out14p out14n vddio_d1 out16 out15 vddio_s1 vdd vdd in2n in2p in1n in1p vdd xin xout dnu vdd vdd 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 vdd vdd sclk sdat fs2 fs1 fs0 vdd vccd xres vin vdd 36 35 34 33 32 31 30 29 28 27 26 25 out21p out21n out22p out22n out23p out23n out24p out24n vddio_d2 out26 out25 vddio_s2 13 14 15 16 17 18 19 20 21 22 23 24
document number: 001-89074 rev. *k page 13 of 29 cy27410 electrical specifications exceeding maximum ratings may short en the useful life of the device. absolute maximum ratings operating temperature operating power supply table 4. absolute maximum ratings symbol description conditions min typ max units v dd core supply voltage ?0.5 ? 4.6 v v ddiox output bank supply voltage ?0.5 ? 4.6 v v in input voltage relative to v ss ?0.5 ? v dd + 0.4 v v ini2c i2c bus input voltage sclk, sdat pins ?0.5 ? 6 v t s storage temperature non functional ?55 ? +150 c esd hbm esd (human body model) jedec js-001-2012 2000 ? ? v esd cdm esd (charged device model) jedec jesd22-c101e 500 ? ? v esd mm esd (machine model) jedec jesd22-a115b 200 ? ? v lu latchup jedec jesd78d ? ? 140 ma ul-94 flammability rating v-0 at 1/8 in ? ? 10 ppm msl moisture sensitivity level ? 3 ? ? ja package thermal resistance pcb dimensions 76x114x1.6mm, 4 layers, 0 air flow 13 c/w table 5. operating temperature symbol description conditions min typ max units t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c table 6. operating power supply symbol description conditions min typ max units v dd core supply voltage 1.8-v range: 5% 1.71 1.80 1.89 v 2.5-v range: 10% 2.25 2.50 2.75 v 3.3-v range: 5% 3.13 3.3 3.46 v v ddio output supply voltage 1.8-v range: 5% 1.71 1.80 1.89 v 2.5-v range: 10% 2.25 2.50 2.75 v 3.3-v range: 5% 3.13 3.30 3.46 v i ddo power supply current per pair l vpecl, output pair terminated 50 ? to v tt (v dd ? 2 v) ? ? 38.0 ma lvpecl, output pa ir terminated 50 ? to v tt (v dd ? 1.7 v) ? ? 27.0 ma i ddo power supply current per pair lv ds, output pair terminated 100 ? ? ? 13.25 ma i ddo power supply current per pair hcsl, output pair terminated 33 ? to 49.9 ? to gnd ? ? 26.5 ma i ddo power supply current per pair cml, output pair terminated 50 ? to v dd ? ? 18.0 ma i ddo power supply current per pair cmos, 10-pf load, 33 mhz ? ? 6.0 ma i ddpll1 current consumption per pll includes divc ? ? 26.5 ma i ddxo xo/input block current consumption xo or in1 input buffer on, in2 input buffer off ? ? 3.5 ma
document number: 001-89074 rev. *k page 14 of 29 cy27410 dc chip-level specifications i ddpm power management block current consumption ? ? 2.5 ma t plllock pll lock time time from pll enabled to pll stable (pll reaches at 1-ppm accuracy) ? ? 250 ? s t lock device power-up time time from minimum specified v dd to output stable in xo-based clock gen mode. in the case of external clock input, t lock will reduce by the crystal oscillator startup time (t oscstart ). this specification is valid when the reference is available and stable at startup. for supply ramps slower than the t pu_sr spec where customers use xres during power up. power-up time will be calculated from the release of xres to output stable. ? ? 10.0 ms t oscstart crystal oscillator startup time time from crystal oscillator power-up to crystal oscillator stable. crystal fnom = 25 mhz, c1>1 ff ? ? 4 ms t pu_sr power supply slew rate during power up power-supply ramp rate for v dd to reach minimum specified voltage (power ramp must be monotonic). for supply ramps slower than 1 v/ms, use xres to externally keep the part in reset during power-up and release xres after v dd reaches the minimum specification. 1 ? 67 v/ms table 7. dc electrical specifications input symbol description conditions min typ max units v ih33 input high voltage lvcmos and logic inputs, v dd = 3.3 v 2.0 ? ? v v ih25 input high voltage lvcmos and logic inputs, v dd = 2.5 v 1.7 ? ? v v ih18 input high voltage lvcmos and logic inputs, v dd = 1.8 v 1.1 ? ? v v il33 input low voltage lvcmos and logic inputs, v dd = 3.3 v ? ? 0.8 v v il25 input low voltage lvcmos and logic inputs, v dd = 2.5 v ? ? 0.7 v v il18 input low voltage lvcmos and logic inputs, v dd = 1.8 v ? ? 0.5 v v diff differential input lvds, cml, pecl, hc sl. differential amplitude, pk. 0.30 ? 1.45 v dc diff duty cycle, differential input measured at crossing point 40 50 60 % dc lvcmos duty cycle, lvcmos input measured at 1/2 v dd 40 50 60 % i ih input high current input = v dd ? ? 150 ? a i il input low current input = gnd ?150 ? ? ? a c in input capacitance, in1, in2 measured at 10 mhz, differential ? ? 3.0 pf v ppsine ac input swing pk clipped sine wave, ac coupled through a 1000-pf capacitor. 0.8 1.0 1.2 v r p input pull-down resistance lvcmos input 75 115 170 k ? table 6. operating power supply (continued) symbol description conditions min typ max units
document number: 001-89074 rev. *k page 15 of 29 cy27410 dc output specifications table 8. dc specifications for lvcmos output symbol description conditions min typ max units v oh output high voltage 4-ma load v ddio ? 0.3 ? ? v v ol output low voltage 4-ma load ? ? 0.3 v table 9. dc specifications for lvds output (v ddio = 2.5-v or 3.3-v range) symbol description conditions min typ max units v pp lvds output ac single-ended pk-pk, 8 mhz to 325 mhz 250 ? 510 mv v pp lvds output ac single-ended pk-pk 325 mhz to 700 mhz 200 ? 510 mv ? v pp change in v pp between complementary output states ??50mv v ocm output common-mode voltage met only at 2.5 v and 3.3 v. need ac coupling for 1.8-v operation 1.125 1.200 1.375 v ? v ocm change in vocm between complementary output states ??50mv i oz output leakage current output off, v out = 0.75 v to 1.75 v ?20 ? 20 ? a table 10. dc specificatio ns for lvpecl output (v ddio = 2.5-v or 3.3-v range) symbol description conditions min typ max units v oh output high voltage r-term = 50 ? to v tt (v ddio ? 2.0 v) v ddio ? 1.165 ? v ddio ? 0.800 v v ol output low voltage r-term = 50 ? to v tt (v ddio ? 2.0 v) v ddio ? 2.0 ? v ddio ? 1.620 v v pp lvpecl output ac single ended pk-pk, f out = 8 mhz to 150 mhz 450 ? ? mv f out = 150 mhz to 700 mhz 320 ? ? mv table 11. dc specifications for cml output (v ddio = 2.5-v or 3.3-v range) symbol description conditions min typ max units v oh output high voltage r-term= 50 ? to v ddio v ddio ? 0.1 ? ? v v ol output low voltage r-term= 50 ? to v ddio v ddio ? 0.7 ? v ddio ? 0.3 v v pp cml output ac single-ended pk-pk f out = 8 mhz to150 mhz 250 ? 700 mv v pp cml output ac single-ended pk-pk 150 < f out < 700 mhz 200 ? 600 mv
document number: 001-89074 rev. *k page 16 of 29 cy27410 ac input clock specifications ac output specifications table 12. dc specifications for hcsl output (v ddio = 2.5-v or 3.3-v range) symbol description conditions min typ max units v ocm output common mode voltage common mode 350 ?400mv v ohdiff differential output high voltage measurement taken from differential waveform 150 ??mv v oldiff differential output low voltage measurement taken from differential waveform ? ? ?150 mv v cross absolute crossing point voltage measurement taken from single-ended waveform 250 ?550mv v crossdelta variation of v cross over all rising clock edges measurement taken from single-ended waveform ? ?140mv table 13. input frequency range symbol description conditions min typ max units f crystal crystal frequency fundamental at cut crystal 8 ? 48 mhz f reference reference frequency internal reference to pll 8 ? 40 mhz f incmos lvcmos input frequency buffer mode, all plls off 8 ? 250 mhz f incmos lvcmos input frequency buffer mode, one or more pll active 8 ? 125 mhz f incmos lvcmos input frequency clkgen mode 8 ? 250 mhz f incmos lvcmos input frequency zdb mode, pll in integer n configuration 8 ? 250 mhz f indiff differential clock input frequency buffer mode, all plls off 8 ? 700 mhz f indiff differential clock input frequency buffer mode, one or more pll active 8 ? 125 mhz f indiff differential clock input frequency clkgen mode 8 ? 300 mhz f indiff differential clock input frequency zdb mode, pll in integer n configuration 8 ? 300 mhz f incas cascading clock frequency internal cascading frequency in the buffer mode 8 ? 125 mhz table 14. ac input cloc k electrical specification symbol description conditions min typ max units t cmosdc lvcmos input duty cycle measured at 1/2 v dd 20%?80%, functional 40 50 60 % t diffdc differential input duty cycle measured at v ocm 20%?80%, functional 40 50 60 ? t rfcmos lvcmos input rise/fall time measured between 20%?80% of v dd ??4ns table 15. ac electrical specifications lvcmos outp ut. load: 15 pf < 100mhz, 7.5 pf < 200 mhz, 5 pf > 200 mhz symbol description conditions min typ max units common ac electrical specifications t rfcmos rise/fall time f out < 100mhz, 20%?80% ? ? 2.0 ns t rfcmos rise/fall time f out < 200mhz, 20%?80% ? ? 1.5 ns t rfcmos rise/fall time f out < 250mhz, 20%?80% ? ? 1.3 ns t skew output to output skew equally loaded, measured at 1/2 v iox , in a bank, derived from the same pll, ? ? 150 ps buffer mode f out output frequency all plls off 8 250 mhz f out output frequency with one or mo re pll running 8 125 mhz
document number: 001-89074 rev. *k page 17 of 29 cy27410 t dc output duty cycle measured at 1/2 v iox . input dc = 50% 40 50 60 % t jit_add additive rms phase jitter f out = 156.25 mhz, 12k-20 mhz offset, divi=1.input slew rate 1.8 v/ns 20%?80% v dd ? 0.7 1.0 ps t delay propagation delay input to output delay ? ? 7.0 ns zdb mode (in1 = ref, differenti al or lvcmos feedback to in2) f out output frequency 8 ? 250 mhz t dc output duty cycle measured at 1/2 v iox, f out > 200 mhz, v ddio = 2.5 v or 3.3 v. f out > 100mhz, v ddio = 1.8 v 40 50 60 % t dc output duty cycle measured at 1/2 v iox, f out ? 200 mhz v ddio = 2.5 v or 3.3 v. f out ? 100 mhz, v ddio = 1.8 v 45 50 55 % t occj cycle-to-cycle jitter pk, measured at 1/2 v iox over 10-k cycle, f out = 100 mhz.input slew rate 1.8v/ns 20%?80% v dd . configuration dependent ? ? 50 ps t pj period jitter pk-pk, measured at 1/2 v iox over 10-k cycle, f out = 100 mhz.input slew rate 1.8 v/ns 20%?80% v dd . configuration dependent ? ? 100 ps t pdelay propagation delay measured at 1/2 v iox 250 ps excludes any delay added onboard (from output to inputs). delay onboard (t delay_board ) must not exceed 2-ns max. total delay in the zdb mode is t delay_board + t pdelay ?350 ? 350 ps clkgen mode f out output frequency 3 ? 250 mhz f outl low frequency output 1 khz is supported when the max input frequency to divl is 48 mhz 0.001 ? 50 mhz t dc output duty cycle measured at 1/2 v iox, f out > 200 mhz, v ddio = 2.5 v or 3.3 v. f out > 100 mhz, v ddio = 1.8 v 40 50 60 % t dc output duty cycle measured at 1/2 v iox, f out ?? 200 mhz v ddio = 2.5 v or 3.3 v. f out ? 100 mhz, v ddio = 1.8 v 45 ? 55 % t ccj cycle-to-cycle jitter pk, measured at 1/2 v iox over 10-k cycle, f out =100 mhz. configuration dependent ? ? 50 ps t pj period jitter pk-pk, measured at 1/2 v iox over 10-k cycle, f out = 100 mhz. input reference 25-mhz crystal. configuration dependent ? ? 100 ps ssc mode f out output frequency 3 ? 250 mhz t dc output duty cycle measured at 1/2 v iox, f out > 200 mhz, v ddio = 2.5 v or 3.3 v. f out > 100 mhz, v ddio = 1.8 v 40 50 60 % t dc output duty cycle measured at 1/2 v iox , f out ? 200 mhz v ddio = 2.5 v or 3.3 v. f out ? 100 mhz, v ddio = 1.8 v 45 50 55 % t ccj cycle-to-cycle jitter pk, measured at 1/2 v iox over 10-k cycle, f out = 100 mhz, with a spread of 0.5%. input reference 25-mhz crystal. configuration dependent ? ? 100 ps table 15. ac electrical specifications lvcmos output . load: 15 pf < 100mhz, 7.5 pf < 200 mhz, 5 pf > 200 mhz (continued) symbol description conditions min typ max units
document number: 001-89074 rev. *k page 18 of 29 cy27410 table 16. ac electrical specifications, di fferential output (lvpecl, cml, lvds) [1] symbol description conditions min typ max units common ac electrical specifications t rf pecl output rise/fall time 20%?80% of ac levels, measured at 622.08 mhz ? ? 450 ps t rf cml output rise/fall time 20%?80% of ac levels, measured at 622.08 mhz ? ? 450 ps t rf lvds output rise/fall time 20%?80% of ac levels, measured at 622.08 mhz ? ? 450 ps t sk1 output skew four differential output pairs in a bank, derived from the same pll, with same standard and load conditions ? ? 100 ps buffer mode t odc output duty cycle differential input signal at 50% duty cycle, differential signal, 622.08 mhz 45 50 55 % t odc output duty cycle lvcmos input signal at 50% duty cycle, differential signal, 250 mhz 40 50 60 % t pd propagation delay measured at differential signal, 156.25 mhz ? ? 4 ns t jit_add additive rms phase jitter f out = 156.25 mhz, 12-k to 20-mhz offset, div1 = 1. input slew rate 4 v/ns differential 400-mv amplitude. ? ? 400 fs zdb mode (ref=in1, 1 pair of output is feedback to in2) t odc output duty cycle measured at differential signal, 100 mhz 45 50 55 % t ccj cycle-to-cycle jitter pk, measured differential signal over 10-k cycle, f out =156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. (all differential outputs on) ? ? 50 ps t pj period jitter pk-pk, measured differential signal over 10-k cycle, f out = 156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. (all differential outputs on) ? ? 50 ps t pd propagation delay measured differential signal, f out = 156.25 mhz, 250 ps is excluding any delay added onboard (from output to inputs). delay onboard (t delay_board ) must not exceed 2-ns max. total delay in the zdb mode is t delay_board + t pdelay ?300 ? 300 ps t jrms rms phase jitter f in = f out = 156.25 mhz, 12-k to 20-mhz offset. input slew ra te 4 v/ns differential 400-mv amplitude ? 0.7 1.0 ps png10k phase noise, offset = 10 khz f in = f out = 156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. ? ? ?110 dbc/ hz png100k phase noise, offset = 100 khz f in = f out = 156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. ? ? ?119 dbc/ hz png1m phase noise, offset = 1 mhz f in = f out = 156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. ? ? ?131 dbc/ hz png10m phase noise, offset = 10 mhz f in = f out = 156.25 mhz. input slew rate 4 v/ns differential 400-mv amplitude. ? ? ?147 dbc/ hz note 1. ac parameters for differential outputs are guaranteed for only differential outputs. lvcmos is off.
document number: 001-89074 rev. *k page 19 of 29 cy27410 pn-spur spur at frequency offsets equal to and greater than the update rate of the pll. input slew rate 4 v/ns differential 400-mv amplitude. ? ? ?65 dbc/ hz clkgen mode t odc output duty cycle measured at differential signal, 622.08 mhz 45 50 55 % t ccj cycle-to-cycle jitter pk, measured at differential signal, 156.25 mhz, over 10-k cycles. input frequency (24 mhz to 40 mhz) crystal. (all differential outputs on) ? ? 50 ps t pj period jitter pk-pk, measured at differential signal 156.25 mhz, over 10-k cycles. input frequency (24 mhz to 40 mhz) crystal. (all differential outputs on) ? ? 50 ps t jrms rms phase jitter f out = 156.25 mhz, 12-k to 20-mhz offset ? 0.7 1.0 ps png10k phase noise, offset = 10 khz f out =156.25 mhz. input reference 25-mhz crystal ? ? ?110 dbc/ hz png100k phase noise, offset = 100 khz f out =156.25 mhz. input reference 25-mhz crystal ? ? ?119 dbc/ hz png1m phase noise, offset = 1 mhz f out = 156.25 mhz. input reference 25-mhz crystal ? ? ?131 dbc/ hz png10m phase noise, offset = 10 mhz f out = 156.25 mhz. input reference 25-mhz crystal ? ? ?147 dbc/ hz pn-spur spur at frequency offsets equal to and greater than the update rate of the pll ? ? ?65 dbc/ hz ssc mode t ccj cycle-to-cycle jitter pk, measured at differential signal, 156.25 mhz, over 10-k cycles. input frequency (24 mhz to 40 mhz) crystal, with a spread of 0.5% (all differential outputs on). ? ? 70 ps table 16. ac electrical specifications, di fferential output (lvpecl, cml, lvds) [1] (continued) symbol description conditions min typ max units table 17. ac electrical specification hscl output [2, 3] symbol description conditions min typ max units common ac electrical specifications f oc output frequency hcsl 96 ? 400 mhz e r rising edge rate measurement taken from differential waveform, ?150 mv to +150 mv 0.6 ? 4 v/ns e f falling edge rate measurement taken from differential waveform, ?150 mv to +150 mv 0.6 ? 4 v/ns t stable time before v rb is allowed measurement taken from differential waveform, ?150 mv to +150 mv 500 ? ? ps t period_avg average clock period accuracy, 100 mhz measurement taken from differential waveform, spread spectrum on, 0.5% down spread ?300 ? 2800 ppm t period_abs absolute period, 100 mhz measurement taken from differential waveform, spread spectrum on, 0.5% down spread 9.874 ? 10.203 ns notes 2. ac parameters for differential outputs are guaranteed for only differential outputs. lvcmos is off. 3. all output clocks 100mhz hcsl format. jitter is from pcie jitter filter combination that produces the highest jitter.
document number: 001-89074 rev. *k page 20 of 29 cy27410 r-f matching rise-fall matching measurement taken from single-ended waveform. rising edge rate to falling edge rate matching 100 mhz ?20 ? +20 % buffer mode t dc duty cycle measurement taken from differential waveform 45 50 55 % t rms_add additive phase noise input slew rate 4 v/ns differential 400-mv amplitude. ? ? 0.4 ps (rms) zdb mode (ref = in1, 1 outp ut pair fed back to in2) t dc duty cycle measurement taken from differential waveform 45 50 55 % t ccjitter cycle-to-cycle jitter pk, measured at differential signal 100 mhz, over 10-k cycles. input slew rate 4 v/ns differential 400-mv amplitude (all differential outputs on). ? ? 50 ps j rms random jitter pcie 3.0 common clocked pcie gen3 filters. input slew rate 4 v/ns differential 400-mv amplitude. ? 0.7 1.0 ps (rms) t pd propagation delay early/late option is off ?300 ? 300 ps clkgen mode t dc duty cycle measurement taken from differential waveform 45 50 55 % t ccjitter cycle-to-cycle jitter pk, measured at differential signal, 100 mhz, over 10-k cycles. input frequency (24 mhz?40 mhz) crystal (all differential outputs on). ? ? 50 ps j rms random jitter pcie 3.0 common clocked ref = 25-mhz crystal, f out = 100 mhz, pcie gen3 filters ? 0.7 1.0 ps table 17. ac electrical specification hscl output [2, 3] (continued) symbol description conditions min typ max units table 18. ac i 2 c specifications symbol description conditions min typ max units f sck sck clock frequency 0 ? 400 khz t hd:sta hold time start condition 0.6 ? ? ? s t low low period of the sck clock 1.3 ? ? ? s t high high period of the sck clock 0.6 ? ? ? s t su:sta setup time for a repeated start condition 0.6 ? ? ? s t hd:dat data hold time 0 ? ? ? s t su:dat data setup time 100 ? ? ns t r rise time ? ? 300 ns t f fall time ? ? 300 ns t su:sto setup time for stop condition 0.6 ? ? ? s t buf bus-free time between stop and start conditions 1.3 ? ? ? s
document number: 001-89074 rev. *k page 21 of 29 cy27410 table 19. spread-spectrum specifications symbol description conditions min typ max units f mod modulation rate 30 ? 60 khz ssper spread spectrum amount to ta l % 0.1 ? 5.0 % ssstep spread spectrum% step ? 0.1 ? % table 20. output selection specifications symbol description conditions min typ max units t fs frequency switching time frequency switching time for out13,14, 23, 24. both plls are active (change mux selection bit). ? ? 500 s t fs frequency switching time frequency switching time for all outputs, divo value change ? ? 500 s t fs frequency switching time frequency switching time for all outputs. pll value change. ? ? 1000 s t fs output turn-on time output turn-on time from fs. pll is active, change oe or mux. ? ? 500 s t fs output turn-on time output turn-on time from fs. resume pll from power down. ? ? 1000 s t off output turn-off time output turn-off time from fs. pll is active, change oe or mux. ? ? 500 s table 21. nv memory specification symbol description conditions min typ max units dret nv memory data retention 10 ? ? years prog cycle programming cycle programming cycle for nv memory 100 k ? ? cycle table 22. miscellaneous specifications symbol description conditions min typ max units t xres xres low time 10 ? ? s t prog flash programming temperature 5 ? 55 c c inadc input capacitance vin pin ? ? 10 pf
document number: 001-89074 rev. *k page 22 of 29 cy27410 test and measurement circuits figure 23. lvpecl output load and test circuit f igure 24. lvds output load and test circuit figure 25. cml output load and test circuit fig ure 26. hcsl output load and test circuit figure 27. lvcmos output load and test circuit tp tp v ddio ? 2 v buf 50 ? 50 ? v ddio 50 ? 50 ? tp tp buf 100 ? v ddio 50 ? 50 ? tp tp v ddio buf 50 ? 50 ? 50 ? v ddio 50 ? tp tp buf 33 ? 33 ? v ddio 49.9 ? 49.9 ? 5? 2 pf 2 pf 50 ? 50 ? tp buf v ddio c load
document number: 001-89074 rev. *k page 23 of 29 cy27410 voltage and timing definitions figure 28. lvcmos input definitions figure 29. lvcmos output definitions figure 30. differential input definitions figure 31. diffe rential output definitions figure 32. skew definition figure 33. propagation delay definition figure 34. output enable/disable/frequency select timing figure 35. hcsl single-ended measurement point-2 figure 36. hcsl differential measurement point figur e 37. hcsl differential measurement for ringback 50% of v dd clock 20% of v dd 80% of v dd t1 t2 t r t f t dc = t1 / (t1 + t2) v ih v il 50% of v iox out 20% of v iox 80% of v iox t1 t2 t r t f t odc = t1 / (t1 + t2) v oh v ol t pw t period v pp id clock-p clock-n v a v b v ocm = (v a + v b ) / 2 t dc = t pw / t period t pw t period v pp out-p out-n v a v b v ocm = (v a + v b ) / 2 t dc = t pw / t period 80% 20% 80% 20% t f t r t sk1 outx outy outx outy 50% of v iox 50% of v iox v ocm v ocm t pd inx outy inx outy 50% of v iox 50% of v iox v ocm v ocm fs clock original ? clock new ? clock t off t fs rise and fall time matching v cross ? median ? out \ n out \ p v cross ? median ? +75 ? mv v cross ? median ?\ 75 ? mv v cross ? median ? out \ n out \ p t fall t rise duty cycle and period clock ? period ? (differential) positive ? duty cycle ? (differential) negative ? duty cycle ? (differential) 0.0 ? v out \ p ? + out \ n v ih ? = ? +150 ? mv v rb ? = ? +100 ? mv v rb ? = ?\ 100 ? mv v il ? = ?\ 150 ? mv out \ p ? + out \ n t stable t stable v rb v rb
document number: 001-89074 rev. *k page 24 of 29 cy27410 figure 38. hcsl rise and fall time figure 39. power ramp and pll lock time figure 40. definition for timing for fast/standard mode on the i 2 c bus v ih ? = ? +150 ? mv v il ? = ?\ 150 ? mv 0.0 ? v out \ p ? + out \ n rising ? edge ? rate falling ? edge ? rate rise and fall time supply voltage output stable output v dd (min) 0.5 v t pu t lock sdat sclk s sr p s t f t r t low t hd;sta t hd;dat t high t su;dat t f t su;sta t hd;sta t su;sto t r t buf
document number: 001-89074 rev. *k page 25 of 29 cy27410 packaging information this section illustrates the packaging sp ecifications for the cy27410 device, along with the thermal impedances for each packag e. important note the epad must be connected to ground to reduc e the thermal resistance and for signaling ground. figure 41. 48-pin qfn (7 7 1.00 mm) lt48d 5.5 x 5.5 epad (sawn) package outline for information on the preferred dimensions for mounting qfn packages, refer to the cypress application note an72845 - design guidelines for cypress quad flat no extended lead (qfn) packaged devices . solder reflow specifications ta b l e 2 3 shows the solder reflow temperature limits that must not be exceeded. 001-45616 *e table 23. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 48-pin qfn 260 ? c 30 seconds
document number: 001-89074 rev. *k page 26 of 29 cy27410 ordering information the following table lists the cy27410 device?s key package features and ordering codes. ordering code definitions table 24. ordering information part number configuration package production flow CY27410FLTXI field programmable 48-pin qfn industrial, ? 40 c to +85 c CY27410FLTXIt field programmable 48-pin qfn tape and reel industrial, ? 40 c to +85 c cy27410ltxi?xxx factory configured 48-pin qfn industrial, ? 40 c to +85 c cy27410ltxi?xxxt factory configured 48-pin qfn tape and reel industrial, ? 40 c to +85 c tape and reel customer part configuration code temperature range: i = industrial pb-free: x= pb free package type: lt: 48-pin qfn configuration: f= field programmable, blank= factory configured marketing code: 274xx = device number company id: cy = cypress 27410 f lt ? xxx cy i t x
document number: 001-89074 rev. *k page 27 of 29 cy27410 acronyms document conventions units of measure table 25. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cml current-mode logic cmos complementary metal oxide semiconductor dc direct current esd electrostatic discharge fs frequency select gui graphical user interface hcsl high-speed current steering logic i 2 c inter-integrated circuit i/o input/output issp in-system serial programming jedec joint electron devices engineering council ldo low dropout (regulator) lsb least-significant bit lvcmos low voltage complementary metal oxide semicon- ductor lvds low-voltage differential signals lvpecl low-voltage positive emitter-coupled logic msb most-significant byte nv non-volatile nzdb non-zero delay buffer oe output enable pcie pci express por power-on reset psoc ? programmable system-on-chip qfn quad flat no-lead rms root mean square sclk serial i 2 c clock sdat serial i 2 c data tssop thin shrunk small outline package usb universal serial bus xtal crystal zdb zero delay buffer table 26. units of measure symbol unit of measure c degree celsius dbc decibels relative to the carrier ff femtofarad fs femtosecond g gram ghz gigahertz hz hertz khz kilohertz ksps kilo samples per second k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? w microwatt ma milliampere ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond nv nanovolt ? ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ppb parts per billion ps picosecond sps samples per second ? sigma: one standard deviation v volt w watt
document number: 001-89074 rev. *k page 28 of 29 cy27410 document history page document title: cy27410, 4-pll spread-spectrum clock generator document number: 001-89074 rev. ecn orig. of change submission date description of change *g 4866820 bpin 07/31/2015 final data sheet for web release. *h 4889775 xht 08/19/2015 updated features : replaced ?75-ps skew? with ?100-ps skew?. *i 4930976 xht 09/23/2015 updated functional description : updated input system : updated description. *j 5090700 xht 01/18/2016 changed ordering information changed ordering code definitions added factory configured part number removed es identifier *k 5351208 xht 07/14/2016 updated cy logo and disclaimer.
document number: 001-89074 rev. *k revised july 14, 2016 page 29 of 29 cy27410 ? cypress semiconductor corporation, 2013-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

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